1. Field of the Invention
The present invention relates to communication systems, in particular, to operations for testing encryption and decryption datapaths of an accelerated processor architecture for packet networks.
2. Description of the Related Art
Network processors are generally used for analyzing and processing packet data for routing and switching packets in a variety of applications, such as network surveillance, video transmission, protocol conversion, voice processing, and internet traffic routing. Early types of network processors were based on software-based approaches with general-purpose processors, either singly or in a multi-core implementation, but such software-based approaches are slow. Further, increasing the number of general-purpose processors diminished performance improvements, or actually slowed down overall network processor throughput. Newer designs add hardware accelerators to offload certain tasks from the general-purpose processors, such as encryption/decryption, packet data inspections, and the like. These newer network processor designs are traditionally implemented with either i) a non-pipelined architecture or ii) a fixed-pipeline architecture.
In a typical non-pipelined architecture, general-purpose processors are responsible for each action taken by acceleration functions. A non-pipelined architecture provides great flexibility in that the general-purpose processors can make decisions on a dynamic, packet-by-packet basis, thus providing data packets only to the accelerators or other processors that are required to process each packet. However, significant software overhead is involved in those cases where multiple accelerator actions might occur in sequence. In a typical fixed-pipeline architecture, packet data flows through the general-purpose processors and/or accelerators in a fixed sequence regardless of whether a particular processor or accelerator is required to process a given packet. This fixed sequence might add significant overhead to packet processing and has limited flexibility to handle new protocols, limiting the advantage provided by using the accelerators.
Network processors implemented as a system on chip (SoC) having multiple processing modules might typically employ an external memory device to store packet and other data. Some network processors might encrypt data stored on the external memory, thus, the SoC might include an encryption and decryption pipeline for encrypting data for storage on the external memory, and for decrypting data for use by the network processor. The SoC might also employ a non-encrypted pipeline for reading and writing non-encrypted data to and from the external memory. Since it takes relatively longer to send data through the encryption/decryption pipeline than through the non-encrypted pipeline, one or more register stages might be implemented in the encryption/decryption pipeline to buffer data during encryption and decryption operations. Typical debugging operations of the SoC might simply disable encryption/decryption, which might then bypass the encryption logic and register stages, potentially causing signal timing problems or masking problems in the encryption/decryption pipeline. Thus, there is a need for an improved debugging operation of an encryption/decryption pipeline of an SoC.